IBM to release design kits for its 0.7nm Nanostack process in early 2027
The advancement of sub-nanometer lithography opens a new chapter. IBM has confirmed that it will make the first process development kits, known as PDKs, available to semiconductor designers. It will do so for its Nanostack technology. 0.7 nanometers and it will be during first quarter of 2027.
The move will allow companies like NVIDIA or AMD to begin evaluating and adapting their architectures to this node before foundries begin their large-scale commercial deployment.
The company’s proposal, initially presented in June, is equivalent in the industry’s commercial nomenclature to the 7 angstromstaking into account that one nanometer is equivalent to ten angstroms. With current mass production located in the 2 nanometers and alternatives in progress such as the 18A, A16 and A14 nodes from Intel or TSMC, IBM’s initiative seeks to solve critical physical limits in transistor density, energy consumption and, very specifically, in the scale of SRAM memory.
Vertical stacking of transistors and a 40% reduction in SRAM
Kits distributed by IBM will include design rules manuals, automated verification and scripts for electronic design automation (EDA) tools supplied by firms such as Synopsys and Cadence.
According to the sources consulted, the Nanostack architecture is based on stack vertically and staggered N-type (NMOS) and P-type (PMOS) transistors. By being built sequentially rather than contiguous, not only is the physical space of the circuit compacted, but engineers are freed to experiment with differentiated materials in each layer without disturbing the electrical insulation.
This reorganization is especially relevant for integrated memory blocks. Today, as compute logic continues to shrink to 2-nanometer lithographs, SRAM memory cells have barely managed to shrink below 3 nanometers due to leakage current, signal loss, and microscopic scattering of impurities in the silicon. In this way, static memory has remained almost stagnant on the surface while the rest of the processor decreased in size.
IBM’s 7 angstrom node promises a 40% reduction in the area occupied by the SRAM. This advance points directly to modern artificial intelligence accelerators, where the integrated cache devours a critical portion of the silicon.
The same medium recalls that in processors such as the NVIDIA Hopper H100, the SRAM absorbs about 10% of the total surface area of the integrated circuit, a figure that scales up to 12% or 15% if the L1 level memories in the calculation cores are added, competing directly for space with the HBM memory. The availability of these kits in 2027 will serve as a test bed to evaluate whether this architecture manages to alleviate that physical bottleneck or not.
