This is what Huawei’s Ascend chips will look like in 2029: a scale of 384 GB from HBM and up to 28 PFLOPS

The Huawei Connect 2026 that has just been held has already left us the first important data. Data that focuses, above all, on the company’s future in the field of AI hardware. The company has shown what its roadmap will be for the house’s accelerators, the Ascend.

The first thing we have been able to see is that Huawei is in a hurry. Their future architectures could arrive much sooner than expected after, among other things, consolidating an autonomous supply chain in semiconductors. Thus, the Ascend accelerator catalog will advance its next generations between 2027 and 2029. Obviously, the company’s idea is that of the rest of the players in this segment: to cover the demand that currently exists for this type of hardware.

As we already explained to you, in China they are very clear that they need to be self-sufficient. In fact, we recently learned that the firm has already closed the supply of 160,000 units of the Ascend 950DT model to DeepSeek. Everything stays at home, we can say.

Now, the new plan is not limited to renewing individual chips, but integrates advances in stacked memories, integrated photonics and mass storage addressing to optimize training and distributed inference. As part of this strategy, The manufacturer will structure its catalog into four key processors distributed over the next three years.

Ascend Accelerator Family Schedule and Specifications

As stated Wccftechthis is the roadmap that Huawei proposes for its new AI accelerators:

• Ascend 960DT, for the first quarter of 2027. It will be the successor to the 950 with an advance of three quarters over what was expected. It achieves 2 PFLOPS in FP8 format and 4 PFLOPS in FP4 with a SIMD/SIMT architecture supporting adaptive precision data types such as HiF8 and HiF4. It incorporates 288 GB of HBM memory with a bandwidth of 9.6 TB/s and 2.2 TB/s interconnection.
• Ascend 960PR, expected in the third quarter of 2027. In this case, it is a variant focused on high-speed inference tasks that advances its availability by one quarter. It maintains 2 PFLOPS in FP8 and doubles the computing power in FP4 up to 8 PFLOPS, integrating 192 GB of HBM memory at 2.4 TB/s along with 2.2 TB/s link between processors.
• Ascend 970, to be launched in 2028. Architectural evolution scheduled for the next cycle that reaches 3.6 PFLOPS in FP8 precision and 14 PFLOPS in FP4. It has 288 GB of HBM memory with a transfer rate of 14.4 TB/s and an interconnection interface expanded to 4.4 TB/s.
• Ascend 980, due 2029. Finally, this is a high-scale preliminary design with a compute projection of 7.2 PFLOPS at FP8 and 28 PFLOPS at FP4. Its theoretical parameters include 384 GB of HBM memory at 38.4 TB/s of bandwidth and 8 TB/s of interconnection link.

Atlas 960E SuperPoD: NPO optics and up to 16 exaflops of compute

Huawei has also given other news. In this case, they are focused on large-scale infrastructures. The company has revealed the Atlas 960E SuperPoD. This is a liquid-cooled cluster scheduled for the third quarter of 2027. The platform groups 4,096 NPUs under a unified addressing scheme to achieve 8 exaflops in FP8 format and 16 exaflops in FP4. Likewise, it has NPO optical interconnection using the Hi-ONE engine, offering a transmission speed of 7.2 Tbps per unit to replace traditional pluggable transceivers.

The use of approximately 5,500 integrated optical modules cuts electrical consumption by more than 550 kW compared to equivalent deployments. According to internal tests provided by the company, the system offers 2.3 times more performance in training and 2.5 times more in inference for models with 10 billion parameters compared to the previous Atlas 950.

Finally, to reduce the memory load that allows AI models to maintain context, the manufacturer has also shown the OceanStor M900 storage system. The solution integrates the CPU, network card and disk controller using the Lingqu link to communicate the NPUs directly with the SSDs.