TSMC announces A13, N2U and new technologies to boost artificial intelligence
Taking advantage of the 2026 technology symposium being held in North America, TSMC has presented its most advanced technology for the manufacture of semiconductors. This is the A13an evolution of your node A14 which had already been announced last year, and which will allow more compact and efficient designs to be refined to address the demand for computational requirements in the next generation artificial intelligence.
TSMC presents the A13 node with improvements in efficiency and compatibility with A14
This new manufacturing process A13 offers a 6% area savings regarding the process A14. It also has better performance thanks to the optimization of this new design and better energy efficiency. Additionally, the new, more efficient process is compatible with all designs of the A14allowing faster migration for these cutting-edge designs.
Next to this A13, TSMC also presented the platform A12 with Super Power Rail technology which improves feeding from the back into the silicon, ideal for applications Artificial Intelligence and high performance computing. This new node A12 is scheduled to start in the next 2029.
N2U node improves performance and efficiency for AI, mobile and HPC
He has also made known the process N2Uan evolution of its process 2 nanometers with design and technology optimization to increase speed by up to 4%or reduce the power required by up to 10%. This process N2U also shows a logic density improvement of up to 1.03 times with respect to N2P. The new N2U arrives to meet the needs in mobile devices, AI and HPCwith a forecast for its launch in the 2028.
TSMC Drives Advanced Packaging with 3DFabric, CoWoS and SoIC for the AI Era
TSMC also told us during this symposium about its new advanced packaging system 3DFabric and the silicon stacking in 3D. TSMC has also counted as its packaging system CoWoS (Chip on Wafer on Substrate) now has 5.5 reticles and has plans to increase it. CoWoS with 14 reticles will be able to integrate 10 large CPU chips and 20 HBM memory stacks for him 2028expanding the capacity in the 2029. This technology complements the SoW-X (System on Wafer) of 40 reticles which is also planned for 2029.
3D chip stacking technology TSMC-SoIC It will also reach its most advanced technology. SoIC A14 to A14 will be available in the 2029 providing a density of 1.8x larger inter-chip I/O compared to N2 SoIC on N2. This will offer greater bandwidth for communication between the stacked chips.
TSMC-COUPE promises to double efficiency and reduce latency by 10 times in data centers
TSMC is also preparing an important advance in interconnection to data centers with its technology TSMC-COUPE (Compact Universal Photonic Engine)which will reach a milestone in 2026 with the start of production of a solution co-packaged optics (CPO) integrated directly into the chip package. This approach represents a change compared to traditional on-board optical solutions, by bringing optical communication closer to the processor itself.
Thanks to this integration, TSMC manages to double energy efficiency and reduce latency up to 10 timessignificantly improving communication between systems. The technology is based on a 200 Gbps micro-ring modulatora compact and efficient solution designed to accelerate the movement of data between racks within data centers.
TSMC brings its advanced nodes to automotive, robotics and new applications
In the field of automotive and robotics, TSMC continues to advance with technologies designed to meet the demanding requirements of systems such as ADAS and autonomous vehicles, as well as new applications of Physical AIlike humanoid robots. To respond to these needs, the company has announced its process N2Athe first automotive-grade transistor-based nanosheetwhich promises to offer a significant leap in performance and efficiency.
This new node N2A will allow an improvement between the 15% and 20% in speed at the same consumption compared to the current N3Aand is scheduled to complete certification AEC-Q100 in 2028a key standard in the automotive industry. Besides, TSMC has introduced design kits “Auto-Use” inside your PDK N2Pwhich will allow manufacturers to begin product development before the process is fully validated, thus accelerating development cycles.
Advances are already materializing with the node N3Awhich will go into production in 2026. Thanks to the program “N3 Auto Early”customers were able to start their designs from 2023and currently there are more than 10 products in development based on this technology, with the aim of making vehicles more intelligent, efficient and safe.
N16HV process improves efficiency and size in emerging displays and devices
On the other hand, in the specialized technologies segment, TSMC has also taken an important step by introducing its process N16HVwhich carries the technology of high voltage to the FinFET era. This node, planned for 2026is especially aimed at display driversboth on smartphones and emerging devices.
In the case of the display drivers for smartphonesthe process N16HV will allow increasing the density of doors by 41% and reduce consumption by 35% in front of the previous node N28HV. For devices such as smart glasses or “near-eye” screens, this technology will allow reduce chip size by 40% and consumption by more than 20%significantly improving the autonomy and user experience in this type of device.
