China develops GAA transistors with DUV and aims for 3nm equivalent performance

He Institute of Microelectronics of the Chinese Academy of Sciences has charted a path to developing GAA transistors for sub-3 nanometer processes without EUV lithography being the centerpiece. The information describes a route based on DUV equipment, a technology available in China and used for years in semiconductor manufacturing. The most striking technical data is an on-off ratio greater than 500,000 in the tested devices.

It is convenient to separate this result from the manufacture of a complete processor at 3 nm. The work refers to the transistor and the initial part of the process, while a commercial chip requires solving the metal contacts and the numerous interconnection layers later. A production date, yield rate per wafer, or product that will use this technology has also not been reported. For now we are facing a research route, not a node ready to compete in volume.

A GAA transistor made with DUV lithography

GAA corresponds to gate-all-aroundan architecture in which the door surrounds the channel through which the current circulates. This electrostatic control is more precise than in a FinFET design, where the gate covers three faces of a fin. As transistor size decreases, controlling leakage when it is off becomes more difficult. The enveloping structure allows you to continue reducing dimensions without losing control of the channel at the same pace.

The Institute of Microelectronics has been working with GAA devices for years. The Chinese Academy of Sciences published results in 2023 on FishboneFET and TreeFET structures compatible with GAA processesdeveloped to balance the behavior of N- and P-type transistors. The current news moves in another direction: adapting the architecture and the process to obtain electrical performance associated with very advanced nodes using DUV exposure.

The on-off ratio greater than 500,000 indicates that the current in the active state greatly exceeds that circulating with the transistor closed. It is an important measure to assess gate control and leakage, but it does not alone summarize the performance of a node. There is a lack of public data on driving current, effective gate length, consumption, variability, density, frequency, and behavior after integrating millions of devices.

DUV can repeat exposures, at a cost of complexity

The DUV machines They use deep ultraviolet light and have lower resolution than EUV systems. To draw structures smaller than their direct boundary, a factory can split a pattern across multiple masks and repeat exposure, etch, and deposition steps. This multipatterning technique allowed DUV to be prolonged in previous nodes, although it increases the number of operations and requires very precise alignment.

Each additional step introduces opportunities for error. A deviation between masks can alter the geometry of the transistor or a connection, while more operations increase the processing time and can reduce the percentage of valid chips. For that reason, demonstrating a DUV-isolated device is not the same as demonstrating cost-effective fabrication of dense circuits. The Chinese investigation seeks relieve some of that pressure through a geometry that allows certain separations to be expanded without giving up the desired electrical behavior.

The expression “3nm equivalent performance” should be read in that framework. The commercial names of the nodes no longer represent a single and comparable dimension between manufacturers. They bring together density, consumption, speed and different design rules. A transistor can approach the electrical characteristic of a 3nm process and maintain a density typical of a less advanced technology.

The obstacle continues in contacts and interconnections

Manufacturing begins with the front end of line or FEOLwhere transistors are formed on the wafer. The announced result is concentrated in that stage. Then comes the middle of lineresponsible for connecting each transistor with the first metal contacts, and the back end of linewhich builds the wiring layers that communicate the different blocks of the chip.

The report notes that the DUV route is still must resolve the limitations of the MEOL and the metallic layer M0. These structures need very fine and regular pitches to prevent the space saved in the transistor from being lost in the wiring. If the interconnections occupy more surface area, the final density may fall behind what the device’s behavior suggests. Contact resistance, inter-line capacitance and thermal dissipation also play a role.

The figures necessary to judge its industrial viability are also missing: wafer size, number of masks, multipatterning cycles, defects, performance and cost per useful chip. None of the sources consulted credits a 3 nm production line based on this method. The progress shows that China is investigating an alternative to progress with the tools it has access to, but the transition from a functional transistor to a complete process remains open.