AMD and Intel confirm ACE standard to boost AI performance on x86 CPUs

AMD and Intel have officially confirmed the launch of the ACE extensions (Advanced Computing Extensions) for x86 processors, a set of instructions designed to accelerate artificial intelligence and machine learning workloads directly from the CPU. The announcement comes through x86 Ecosystem Advisory Groupthe body that both companies created in 2024 to coordinate the evolution of the x86 architecture without each manufacturer pulling their own weight.

The presentation of ACE extensions is not a minor detail. During recent years, the development of specialized instructions in x86 processors has generated more than one headache for both manufacturers and software developers, especially with the fragmentation left by the different variants of AVX-512. With ACE, AMD and Intel seek to avoid a repeat of that history just as demand for AI computing on CPUs begins to grow.

What are ACE extensions and what problem do they solve?

ACE extensions are, in essence, a standardized set of instructions designed specifically to speed up matrix multiplication and handling of reduced precision data formatstwo of the most common elements in any AI and machine learning workload. This is not a technology exclusive to AMD or Intel, but rather a common standard that both firms have committed to supporting in their future generations of CPUs.

That is precisely the key to the ad.. Being a joint proposal endorsed by the two brands that dominate the x86 processor market, the ACE extensions start with an advantage that other instruction sets of the past did not have: software developers have many more incentives to implement them, since they do not depend on the unilateral decisions of a single manufacturer. If ACE extensions can effectively accelerate these workloads, software vendors will have little reason not to adopt them.

How ACE extensions work on a technical level

According to documentation published by the x86 Ecosystem Advisory Group, ACE extensions extend existing AVX code and scale with new capabilities without replacing what was already there. The set defines matrix multiplication primitives and adds several new functional blocks to the x86 instruction set:

ACE Registration Statuswhich includes tile and block scale records.
Data processing operations which consume the AVX registry entry and operate on the state of the tile registry.
Data transfer operationsresponsible for moving information between the state of the ACE record and the AVX records.
Status and operations for system managementnecessary for the instruction set to work coherently with the rest of the architecture.

Data formats supported by ACE

One of the most relevant aspects of the technical documentation is the list of data formats that the ACE extensions will support from the first moment. Support ranges from basic integer types to very low-precision floating-point formats, specifically designed to speed up inference and training of AI models without increasing power consumption:

INT8: 8-bit integer.
INT32: 32-bit integer.
FP32: SE8M23 format, defined according to the IEEE-754 standard.
BF16: SE8M7 format.
FP16: SE5M10 format.
E8M0– 8-bit unsigned exponent, used in block scale formats that are powers of two.
FP8: 8-bit floating point, defined in the OCP 8-bit floating point (OFP8) specification.
MX FP8: 8-bit floating point formats, in SE5M2 and SE4M3 variants.
MX FP6: 6-bit floating point formats, in SE3M2 and SE2M3 variants.
MX FP4: 4-bit floating point format, in SE2M1 variant.
MX INT8: 8-bit fixed-point fractional format.

This variety of low-precision formats is just what today’s AI models demand, where reducing numerical precision without losing too much accuracy allows more operations to be executed per second and per watt.

Why this joint endorsement is a game-changer

The big difference between ACE extensions and other previous instruction sets is in the shared fallback. As they are endorsed by both AMD and Intel through the x86 Ecosystem Advisory Group, it is unlikely that either company will abandon these instructions in future generations of processors, something that has happened in the past with extensions that ended up being orphaned or limited to a single manufacturer.

This standardization also prevents excessive fragmentation of the x86 market.an issue that plagued the AVX-512 instruction set and its variants for quite some time, creating confusion over which processors supported exactly which subset of features.

At this time, the actual usefulness of ACE extensions outside of the realm of AI and machine learning is unknown, as they are designed specifically to accelerate these types of workloads.. Specific dates have not yet been confirmed nor which processor families from AMD and Intel will be the first to incorporate support for ACE extensions, although both companies have already publicly committed to integrating them into their future generations of CPUs.