IBM breaks the nanometer barrier with a 7 angstrom chip containing almost 100 billion transistors

The race to offer designs silicon with advanced manufacturing technology began when people began to talk about angstroms. We have heard about technology Intel 18A or even of the 14A which would be equivalent to 1.8 and 1.4 nanometers. But IBM has gone further and has presented its first chip with technology sub-1 nanometer in the world, which incorporates transistor architecture with a 0.7 nanometers either 7 angstroms.

IBM introduces first sub-1 nanometer chip with 0.7nm technology

A new milestone that challenges the industry in miniaturizationexceeding the physical limits for manufacturing with this type of nodes. This new chip IBM sub-1nm will integrate almost 100 billion transistors on a chip that does not exceed the size of a athis manages to double the density that IBM offered in its previous chip manufactured with 2 nanometers ago 5 years.

Nanostack architecture and nanosheets to continue scaling density

To achieve this feat, a series of new structural technologies and also materials have been used, where the architecture of three dimensional nanostacking of IBM. With this the manufacturer is able to demonstrate that it is possible to improve current technologies, thus following the path to obtain a better performance and minor energy consumption even in dimensions as small as this.

The figures offered by IBM They continue to be impressive, approaching the 50% more performance and a 70% more energy efficiency Regarding the chips 2 nanometers own. Performance and energy savings that are necessary to continue advancing in current technologies such as Artificial intelligence.

Nanostack, the first 3D design based on nanosheets

This new chip sub-1 nanometer It has the architecture called Nanostackbeing the first three-dimensional design based on nanosheetsa breakthrough in nanosheet technology that was also developed by IBM. This design consists of vertically stack and stagger transistorstaking advantage of sequential integration in 3D to add a greater number of transistors on the same chip, and allowing the use of various materials in each layer.

More scalability for SRAM and heavy AI loads

Going a little further into technology Nanostackthis is achieved through ultrathin dielectric junction in CMOS and the operation of CMOS inverter along with the ability to dual channelwhich offer switching performance consistent with this technology. This design also offers a Up to 40% scalability in SRAMto help deliver faster, more efficient chips along with high bandwidth for the heaviest loads on AI.

IBM hopes to bring this technology to production in about five years

This technology is being developed at the semiconductor research center of Albanyin New Yorkwhich will also soon have a new lithography machine High NA EUV to carry out these projects. IBM believes that it will be possible to carry out this technology in just 5 years.